The present invention relates to semiconductor devices having thereon MIS-type field effect transistors and bipolar transistors, and to a method of fabricating such semiconductor devices. The present invention pertains particularly to ways of increasing the performance and reliability of semiconductor devices by providing improved structures for impurity diffusion layers and gate insulation films.
In a conventional MIS-type field effect transistor in which a gate electrode is formed on a semiconductor substrate with a gate oxide film sandwiched therebetween and impurity diffusion regions (source and drain regions) are formed on opposite sides of the gate electrode, the gate oxide film plays a very important role. There have been strong demands for improved semiconductor devices which are element-miniaturized, which can be driven at low power and which can operate at high speed. However, to meet such requirements while at the same time maintaining high reliability, it is necessary to sophisticatedly contrive not only the physical dimensions of gate oxide films (e.g., the film thickness) but also the structure thereof.
Various techniques for providing improved structures for gate oxide films have been known in the art. In one such technique with a view to improving device reliability, gate oxide layer degradation in function (threshold voltage variation) due to hot carriers of CMOS devices (in particular, hot carriers of nMOS transistors), is controlled, and an oxynitride layer is formed in a gate oxide film. For example, a technique has been reported in a paper (IEDM Tech. Dig. pp. 325-328, IEEE 1993), in which after formation of a gate electrode nitrogen ions are implanted into the gate electrode and into the semiconductor substrate, and the implanted nitrogen is diffused by an annealing treatment to form an oxynitride layer in the gate oxide film. This method is used as an example for describing the steps of forming an oxynitride layer.
In a process step of FIG. 22(a), element isolator 4 is formed in a portion of silicon substrate 1. Thereafter, an oxide film is formed on silicon substrate 1 within an active region surrounded by element isolator 4, and a polysilicon film is deposited. Both the oxide film and the polysilicon film are patterned using photolithography and dry etching, to form gate oxide film 2 and gate electrode 3.
Next, in a process step of FIG. 22(b), an ion implant is carried out in which ions of nitrogen (N+) are implanted, from above the substrate, into gate electrode 3 and into silicon substrate 1 within the active region. The implanted nitrogen ions are then diffused by an annealing treatment, to simultaneously form oxynitride layer 5 in gate oxide film 2, and nitrogen diffusion layer 6 in a near-surface area of silicon substrate 1.
In a process step of FIG. 22(c), ions of arsenic (As+) of low concentration are implanted at approximately right angles to the surface of silicon substrate 1, to form lightly-doped n-type source/drain region 7 at a near-surface area of silicon substrate 1.
In a process step of FIG. 22(d), after deposition of a rather thick silicon oxide film on the substrate an etch back process is carried out to form sidewall 8 on each side surface of gate electrode 3. An ion implant is then performed in which ions of arsenic (A+) of high concentration are implanted at approximately right angles to the substrate, to form heavily-doped n-type source/drain region 9 outside the source/drain region 7.
In so-called "dual gate CMOS device", a gate electrode of an nMOS field effect transistor is n-doped with arsenic while a gate electrode of a PMOS field effect transistor is p-doped with boron.
The above-described technique makes it possible to form miniaturized, low-voltage, fast LDD-type nMOS field effect transistors, and the formation of oxynitride layer 5 in gate oxide film 2 of the transistor controls hot carrier degradation. The aforesaid paper shows that as the dosage of nitride is increased such degradation becomes more controllable. Particularly, nMOS field effect transistors, in which degradation in characteristic caused by hot electron (increase in the threshold voltage) is a critical problem, get much benefit from such hot carrier degradation control.
Additionally, there is produced the effect on the side of the pMOS field effect transistor. More specifically, owing to the formation of the oxynitride layer in the gate oxide film, boron ions are controlled so as not to penetrate to a surface channel region in the substrate, as a result of which the characteristic of transistor is not ill-affected.
The above-described conventional technique, however, suffers some drawbacks. For example, degradation in transistor performance such as transistor drive power drop, was observed to occur due to the formation of oxynitride layer 5 shown in FIG. 22(d). Such a phenomenon may be explained as follows. Because of the formation of oxynitride layer 5, impurity diffusion such as arsenic diffusion and boron diffusion in gate electrode 3 is controlled too much and, as a result, the dual gate structure becomes unable to exhibit its advantages. In addition, there is produced an increase in resistance by gate electrode depletion. Further, it has been reported that the formation of an oxynitride layer in a gate oxide film of a pMOS field effect transistor, decreases transistor mutual conductance for unknown reasons.
Where the characteristics of diffusion layers of transistors are considered, there are still problems other than the aforesaid ones.
In a self-align-silicidation process which is a typical technique for reduction of the resistance of gates and source/drain diffusion layers indispensable to high-speed, high-integration-level MOS devices, it becomes difficult to form a shallow junction when trying to form a stable, low-resistance silicide film to a great thickness in consideration of the fact that silicon (diffusion layer) is consumed at the time of silicide formation. The concentration of impurity at the silicide interface drops and, as a result, parasitic resistance increases. The drain current then decreases.
Such a problem becomes significant when, especially in a surface channel type pMOSFET, ions of BF.sub.2 (boron fluoride) are implanted to form a diffusion layer of the p-type. This gives rise to a new problem. FIG. 23 is a graph showing the boron SIMS profiles of (a) a silicon substrate which has been implanted with BF.sub.2 ions at an implant energy of 30 keV at a dosage of 2.times.10.sup.15 cm.sup.-2 before being subjected to an activation annealing treatment at 1000 degrees centigrade for ten seconds and (b) a silicon substrate which has been implanted with B (boron) ions at an implant energy of 10 keV at a dosage of 2.times.10.sup.15 cm.sup.-2 before being subjected to an activation annealing treatment at 1000 degrees centigrade for ten seconds.
The BF.sub.2 implant is first described. Boron fluoride (BF.sub.2) results from fluoride-boron bounding, which gives rise to dissociation, and there are created two impurity concentration peaks (see FIG. 23). Although the higher of these two peaks is located on the side of the substrate surface, the boron will make no contribution to forming a final diffusion layer, for the boron is present in an area that is silicided later. As a result, the concentration at a silicide/diffusion layer interface decreases from the diffusion layer's original concentration peak, so that the contact resistance of this portion increases. Further, in the case of the surface channel type transistor, when implanting impurities into a diffusion layer, a gate electrode is also implanted with the impurities. Therefore, it becomes necessary to pay attention to the penetration phenomenon in which the impurities penetrate from the gate electrode towards the substrate through a gate insulation film.
FIG. 24 shows the quasi-static C-V characteristic of the BF.sub.2 (boron fluoride) implant (implant energy: 30 kev; dosage: 2.times.10.sup.15 cm.sup.-2) and the B (boron) implant (implant energy: 10 keV; 2.times.10.sup.15 cm.sup.-2). Although no penetration occurs in the case of the B implant, the waveform flat band voltage (Vfb) is 0.86 V. On the other hand, in the case of the BF.sub.2 implant there is a slight shift and the Vfb is 0.88 V, from which it can be seen that somewhat penetration has occurred.
FIG. 25 shows the dependency of the implant dosage of boron and BF.sub.2 upon the flat band voltage. For the case of the BF.sub.2 implant, as the implant energy/dosage increases the shift of the flat band voltage likewise increases, and penetration becomes significant. If a technique, in which a greater implant energy and a greater dosage are used for the purpose of obtaining a greater impurity concentration at the interface between a post-silicide-formation silicide and a diffusion layer, is adopted, this accelerates impurity penetration from gate electrode towards substrate. As a result, it becomes hard to fabricate high-performance transistors.
The above-described problems have been discussed in terms of the BF.sub.2 implant. Although boron penetration from gate electrode to substrate is eased, as compared with the BF.sub.2 implant, in the case of the B implant (see FIGS. 24 and 25), a pn junction between source/drain region and substrate region is formed at a deep location, which is unsuitable for device miniaturization.